SH7706 Datasheet, PDF (137/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
4.2.4 TRAPA Exception Register (TRA)
The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
Bit
31 to 10
9 to 2
1, 0
Bit Name

imm

Initial Value R/W
All 0
R

R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit immediate data
Reserved
These bits are always read as 0. The write value
should always be 0.
4.3 Operation
4.3.1 Reset
The reset sequence is used to power up or restart the SH7706 from the initialization state. The
RESETP signal and RESETM signal are sampled every clock cycle, and in the case of a power-on
reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
reset processing is executed after memory access in progress is completed. The reset sequence
consists of the following operations:
1. The MD bit in SR is set to 1 to place the SH7706 in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions.
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11
to 0 of the EXPEVT register to identify the exception event.
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
Rev. 5.00 May 29, 2006 page 89 of 698
REJ09B0146-0500