SH7706 Datasheet, PDF (316/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request: In this mode a transfer is performed at the transfer request
signal (interrupt request signal) of an on-chip peripheral module. This mode cannot be set in case
of 16-byte transfer. The transfer request signals include 4 signals: the receive data full interrupts
(RXI) and the transmit data empty interrupts (TXI) from serial communication interfaces (SCIF),
the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer
interrupt (CMI) of the CMT. When this mode is selected, if the DMA transfer is enabled (DE = 1,
DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request
signal. The source of the transfer request does not have to be the data transfer source or
destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's
receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source
must be the SCI's transmit data register (TDR). And if the transfer requester is the A/D converter,
the data transfer source must be the A/D data register (ADDR).
Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit
DMA
Transfer
Request
RS3 RS2 RS1 RS0 Source
DMA Transfer Request
Signal
Desti-
Source nation Bus Mode
10 1 0
10 1 1
1 1 0 0 SCIF
TXI2 (SCIF transmit data Any* TDR2 Burst/
transmitter empty interrupt transfer
cycle steal
request)
1 1 0 1 SCIF
RXI2 (SCIF receive data full RDR1 Any* Burst/
receiver interrupt transfer request)
cycle steal
1 1 1 0 A/D
ADI (A/D conversion end
ADDR Any* Burst/
converter interrupt)
cycle steal
1 1 1 1 CMT
CMI (Compare match timer Any*
interrupt)
Any* Burst/
cycle steal
Legend:
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip peripheral module
(excluding DMAC, UBC, and BSC)
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not generated to the CPU.
Rev. 5.00 May 29, 2006 page 268 of 698
REJ09B0146-0500