SH7706 Datasheet, PDF (312/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit
1
0
Note:
Bit Name Initial Value R/W Description
NMIF
0
R/(W)* NMI Flag
NMIF indicates that an NMI interrupt occurred.
This bit is set regardless of whether DMAC is in
operating or halt state. If this bit is set during data
transfer, the transfer on all channels are
suspended. The CPU cannot write 1 to this bit.
Only 0 can be written to clear this bit after 1 is
read.
0: No NMI input. DMA transfer is enabled. (Initial
value)
Clearing condition: Writing NMIF = 0 after NMIF
= 1 read, power-on reset, manual reset
1: NMI input. DMA transfer is disabled.
Setting condition: This bit is set by occurrence
of an NMI interrupt.
DME
0
R/W DMA Master Enable
DME enables or disables DMA transfers on all
channels. If the DME bit and the DE bit
corresponding to each channel in CHCR are set to
1s, transfer is enabled in the corresponding
channel. If this bit is cleared during transfer,
transfers on all the channels can be suspended.
Even if the DME bit is set, transfer is not enabled
if the TE bit is 1 or the DE bit is 0 in CHCR, or the
AE bit is 1 or the NMIF bit is 1 in DMAOR.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
* Only 0 can be written to the AE and NMIF bits after 1 is read.
Rev. 5.00 May 29, 2006 page 264 of 698
REJ09B0146-0500