SH7706 Datasheet, PDF (395/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 13 Realtime Clock (RTC)
13.3.9 Second Alarm Register (RSECAR)
The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB
bit is set to 1, a comparison with the RSECCNT value is performed. From among the
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an RTC alarm interrupt is generated.
The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized by a power-on reset or manual reset, or in standby mode.
Bit
7
6 to 4
3 to 0
Bit Name



Initial Value R/W
0
R/W

R/W

R/W
Description
Second Alarm Enable
0: No compared
1: Compared
Setting value for 10-unit of second alarm in the
BCD-code.
The range can be set from 0 to 5 (decimal).
Setting value for 1-unit of second alarm in the
BCD-code.
The range can be set from 0 to 9 (decimal).
13.3.10 Minute Alarm Register (RMINAR)
The minute alarm register (RMINAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB
bit is set to 1, a comparison with the RMINCNT value is performed. From among the
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an RTC alarm interrupt is generated.
The range of minute can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set.
The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are
not initialized by a power-on reset or manual reset, or in standby mode.
Rev. 5.00 May 29, 2006 page 347 of 698
REJ09B0146-0500