SH7706 Datasheet, PDF (51/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

1.2 Block Diagram
Section 1 Overview
MMU
TLB
CCN
CACHE
BRIDGE
CPU
UBC
AUD
SCI
TMU
RTC
H-UDI
INTC
CPG/WDT
BSC
DMAC
CMT
SCIF
ADC
DAC
External bus
interface
I/O port
Legend:
ADC
: A/D converter
DMAC : Direct memory access controller
AUD
: Advanced user debugger
H-UDI : User debugging interface
BSC
: Bus state controller
INTC : Interrupt controller
CACHE : Cache memory
MMU : Memory management unit
CCN
: Cache memory controller
RTC : Realtime clock
CMT
: Compare match timer
SCI : Serial communication interface (with smart card interface)
CPG/WDT : Clock pulse generator/watchdog timer SCIF : Serial communication interface (with FIFO)
CPU
: Central processing unit
TLB : Address translation buffer
DAC
: D/A converter
TMU : Timer unit
UBC : User break controller
Figure 1.1 SH7706 Block Diagram
Rev. 5.00 May 29, 2006 page 3 of 698
REJ09B0146-0500