SH7706 Datasheet, PDF (130/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
4.1.2 Exception Processing Vector Addresses
The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from
the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an
offset from the vector base address of H'00000400. The vector address offset for general exception
events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is
H'00000600. The vector base address is loaded into the vector base register (VBR) by software.
The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows
the relationship between the vector base address, the vector offset, and the vector table.
VBR
(Vector base address)
+ Vector offset
H'A000 0000
Vector address
Figure 4.1 Vector Addresses
In table 4.1, exceptions and their vector addresses are listed by exception type, instruction
completion state, relative acceptance priority, relative order of occurrence within an instruction
execution sequence and vector address for exceptions and their vector addresses.
Table 4.1 Exception Event Vectors
Exception Current
Type
Instruction
Reset
Aborted
General
exception
events
Aborted
and retried
Exception Event
Exception Vector
Priority^*1 Order
Address
Vector
Offset
Power-on
1
—
H'A00000000 —
Manual reset
1
—
H'A00000000 —
H-UDI reset
1
—
H'A00000000 —
CPU Address error
2
1
—
(instruction access)
H'00000100
TLB miss
2
2
—
(instruction access)
H'00000400
TLB invalid (instruction 2
3
—
access)
H'00000100
Rev. 5.00 May 29, 2006 page 82 of 698
REJ09B0146-0500