SH7706 Datasheet, PDF (115/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.4.3 MMU Instruction (LDTLB)
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is
0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR
to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the
index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in
PTEH and ASID bits 4 to 0 in PTEH are used as the index number.
Figure 3.8 shows the case where the IX bit in MMUCR is 0.
When an MMU exception occurs, the virtual page number of the virtual address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each
exception according to the rules described in section 3.2.5 MMU Control Register (MMUCR).
Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception
processing routine, TLB entry recording is possible. Any TLB entry can be updated by software
rewriting of PTEH and the RC bits in MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
MMUCR
31
0
9
0
SV 0 0 RC 0 TF IX AT
Index
PTEH register
31
17
VPN
Way selection
12 10 8
0
VPN 0 ASID
PTEL register
31
10
0
PPN
0 V 0 PR SZ C D SH 0
Write
Write
Ways 0 to 3
0 VPN(31 to17)
VPN(11, 10) ASID(7 to 0) V
PPN(31 to 10) PR(1, 0) SZ C D SH
31
Address array
Data array
Figure 3.8 Operation of LDTLB Instruction
Rev. 5.00 May 29, 2006 page 67 of 698
REJ09B0146-0500