SH7706 Datasheet, PDF (603/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 21 User Debugging Interface (H-UDI)
21.3 Register Description
The H-UDI has the following registers. Refer to section 23, List of Registers, for more details of
the addresses and access sizes.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary register (SDBSR)
21.3.1 Bypass Register (SDBPR)
The bypass register is a 1-bit register that cannot be accessed by the CPU. When the SDIR is set to
the bypass mode, the SDBPR is connected between H-UDI pins TDI and TDO.
21.3.2 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its
initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the
H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is
set to this register.
Bit
Bit Name Initial Value R/W Description
15
TI3
1
R Test Instruction Bits
14
TI2
1
R Cannot be written by the CPU.
13
TI1
1
12
TI0
1
R 0000: EXTEST
R ^{0100: SAMPLE/PRELOAD}
0101: Reserved (Setting prohibited)
0110: H-UDI reset negate
0111: H-UDI reset assert
100X: Reserved (Setting prohibited)
101X: H-UDI interrupt
110X: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Bypass mode (initial value)
0001: Recovery from sleep
11 to 0 —
All 1
R Reserved
These bits are always read as 1.
Legend: X: Don't care
Rev. 5.00 May 29, 2006 page 555 of 698
REJ09B0146-0500