SH7706 Datasheet, PDF (371/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
Section 12 Timer Unit (TMU)
This LSI uses a three-channel (channels 0 to 2) 32-bit timer unit (TMU).
Figure 12.1 shows a block diagram of the TMU.
12.1 Feature
The TMU has the following features:
• Each channel is provided with an auto-reload 32-bit down counter
• Channel 2 is provided with an input capture function
• All channels are provided with 32-bit constant registers and 32-bit down counters that can be
read or written to at any time
• All channels generate interrupt requests when the 32-bit down counter underflows
(H'00000000 → H'FFFFFFFF)
• Allows selection between 6 counter input clocks: External clock (TCLK), on-chip RTC output
clock (16 kHz), Pφ/4, Pφ/16, Pφ/64, Pφ/256. (Pφ is the internal clock for peripheral modules.)
Note: See section 10, Clock Pulse Generator (CPG), for more information.
• All channels can operate when this LSI is in software standby mode: When the RTC output
clock is being used as the counter input clock, this LSI is still able to count in software standby
mode.
• Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral
module used has an internal bus width of 16 bits, a time lag can occur between the time when
the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read
value caused by this time lag, a synchronization circuit is built into the TCNT so that the entire
32-bit data in the TCNT can be read at once.
• The maximum operating frequency of the 32-bit counter is 2 MHz on all channels: Operate the
SH7706 so that the clock input to the timer counters of each channel (obtained by dividing the
external clock and internal clock with the prescaler) does not exceed the maximum operating
frequency.
Rev. 5.00 May 29, 2006 page 323 of 698
REJ09B0146-0500