SH7706 Datasheet, PDF (235/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
13 RCD1
0
R/W RAS-CAS Delay
12 RCD0
0
R/W When synchronous DRAM interface is selected as
connected memory, sets the bank active read/write
command delay time.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
11 TRWL1
0
R/W Write-Precharge Delay
10 TRWL0
0
R/W The TRWL bits set the synchronous DRAM write-
precharge delay time. This designates the time
between the end of a write cycle and the next bank-
active command. This is valid only when
synchronous DRAM is connected. After the write
cycle, the next bank-active command is not issued
for the period TPC + TRWL.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: Reserved (Setting prohibited)
9
TRAS1
0
R/W CAS-Before-RAS Refresh RAS Assert Time
8
TRAS0
0
R/W When synchronous DRAM interface is selected as
connected memory, no bank-active command is
issues during the period TPC + TRAS after an auto-
refresh command.
00: 2 cycles
01: 3 cycles
10: 4 cycles
11: 5 cycles
7
RASD
0
R/W Synchronous DRAM Bank Active
Specifies whether synchronous DRAM is used in
bank active mode or auto-precharge mode.
When both areas 2 and 3 are to be connected to
synchronous DRAM, select auto-precharge mode.
0: Auto-precharge mode
1: Bank active mode
Rev. 5.00 May 29, 2006 page 187 of 698
REJ09B0146-0500