SH7706 Datasheet, PDF (145/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
4.5 Usage Note
• Return from exception processing
 Check the BL bit in SR with software. When the SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
 Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction,
branch to the SPC address, and return from exception processing.
• Operation when exception or interrupt occurs while SR.BL = 1
 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is
a request and the reception conditions are satisfied, the interrupt is accepted after the
execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby
mode, however, the interrupt will be accepted even when the BL bit in SR is 1.
NMI is accepted when BLMSK in ICR1 is 1.
 Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined.
Differently from general reset processing, no signal is output from STATUS0 and
STATUS1.
• SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as
shown below:
 Re-executing-type exceptions: The PC of the instruction that caused the exception is set in
the SPC and re-executed after return from exception processing. If the exception occurred
in a delay slot, however, the PC of the immediately prior delayed branch instruction is set
in the SPC. If the condition of the conditional delayed branch instruction is not satisfied,
the delay slot PC is set in SPC.
 Completed-type exceptions and interrupts: The PC of the instruction after the one that
caused the exception is set in the SPC. If the exception was caused by a delayed
conditional instruction, however, the branch destination PC is set in SPC. If the condition
of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in
SPC.
• Initial register values after reset
 Undefined registers
R0_BANK0/1 to R7_BANK0/1, R8 to R15, GBR, SPC, SSR, MACH, MACL, PR
 Initialized registers
VBR = H'00000000
Rev. 5.00 May 29, 2006 page 97 of 698
REJ09B0146-0500