SH7706 Datasheet, PDF (524/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Serial data reception: Figure 16.9 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start reception
1. Receive error handling and break detection:
Read the DR, ER, and BRK flags in SCSSR2
to identify any error, perform the appropriate
Read ORER, PER, FER
flags in SCSSR2
error handling, then clear the DR, ER, and
BRK flags to 0. In the case of a framing
error, a break can also be detected by
reading the value of the RxD2 pin.
Yes
PER = 1 or FER = 1?
2. SCIF status check and receive data read :
No
Error processing
Read the SCSSR2 and check that RDF = 1,
then read the receive data in SCFRDR2, read
Read RDF flag in SCSSR2
1 from the RDF flag, and then clear the RDF
flag to 0. The transition of the RDF flag from
0 to 1 can be identified by an RXI interrupt.
No
RDF = 1?
Yes
Read receive data in SCFRDR2,
and clear RDF flag in
SCSSR2 to 0
3. Serial reception continuation procedure: To
continue serial reception, read at least the
receive trigger set number of receive data
bytes from SCFRDR2, read 1 from the RDF
flag, then clear the RDF flag to 0. The
number of receive data bytes in SCFRDR2
can be ascertained by reading the lower bits
of SCFDR2.
No
All data received?
Yes
Clear RE bit in SCSCR2 to 0
End reception
Figure 16.9 Sample Serial Reception Flowchart (1)
Rev. 5.00 May 29, 2006 page 476 of 698
REJ09B0146-0500