SH7706 Datasheet, PDF (619/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
22.2.2 Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is a read/write 8-bit register that sets the power-down
mode.
Bit
Bit Name Initial Value R/W Description
7
—
0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
6
MDCHG 0
R/W Pin MD5 to MD0 Control
Specifies whether or not pins MD5 to MD0 are
changed in software standby mode. When this bit
is set to 1, the MD5 to MD0 pin values are latched
when returning from software standby mode by
means of a reset or interrupt.
0: Pins MD5 to MD0 are not changed in software
standby mode
1: Pins MD5 to MD0 are changed in software
standby mode
5
MSTP8 0
R/W Module Stop 8
Specifies halting the clock supply to the user break
controller UBC (an on-chip supporting module).
When the MSTP8 bit is set to 1, the supply of the
clock to the UBC is halted.
0: UBC runs
1: Clock supply to UBC is halted
4
MSTP7 0
R/W Module Stop 7
Specifies halting of clock supply to the DMAC (an
on-chip peripheral module). When the MSTP7 bit
is set to 1, the supply of the clock to the DMAC is
halted.
0: DMAC runs
1: Clock supply to DMAC halted
Rev. 5.00 May 29, 2006 page 571 of 698
REJ09B0146-0500