SH7706 Datasheet, PDF (105/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.2.1 Page Table Entry Register High (PTEH)
The page table entry register high (PTEH) consists of a virtual page number (VPN) and ASID.
The VPN is set the VPN of the virtual address at which the exception is generated in case of an
MMU exception or CPU address error exception. When the page size is 4 kbytes, the VPN is the
upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set.
The VPN can also be modified by software. As the ASID, software sets the number of the
currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB
instruction.
Bit
31 to 10
9, 8
7 to 0
Bit Name
VPN

ASID
Initial Value R/W

R/W
All 0
R

R/W
Description
Virtual page number
Reserved
These bits are always read as 0. The write value
should always be 0.
Address space identifier
3.2.2 Page Table Entry Register Low (PTEL)
The page table entry register low register (PTEL) is used to store the physical page number and
page management information to be recorded in the TLB by the LDTLB instruction. The contents
of this register are only modified by a software command.
Bit
31 to 10
9
8
7
6, 5
4
3
2
1
0
Bit Name
PPN

V

PR
SZ
C
D
SH

Initial Value R/W

R/W
0
R

R/W
0
R

R/W

R/W

R/W

R/W

R/W
0
R
Description
Physical page number
Page management information
Refer to section 3.3 TLB Functions.
Rev. 5.00 May 29, 2006 page 57 of 698
REJ09B0146-0500