SH7706 Datasheet, PDF (240/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.10 Area 6 Wait Control (PCMCIA I/F)
A6W3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A6W2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WCR2
A6W1 A6W0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Description
Top Cycle
Burst Cycle
Inserted
Wait
State
WAIT Pin
Number of
States per
One-data
Transfer
WAIT Pin
0
Ignored
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
5
Enabled
6
Enabled
7
Enabled
8
Enabled
9
Enabled
10
Enabled
11
Enabled
12
Enabled
13
Enabled
14
Enabled
15
Enabled
18
Enabled
19
Enabled
22
Enabled
23
Enabled
26
Enabled
27
Enabled
30
Enabled
31
Enabled
34
Enabled
35
Enabled
38
Enabled
39
Enabled
Rev. 5.00 May 29, 2006 page 192 of 698
REJ09B0146-0500