SH7706 Datasheet, PDF (497/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit Bit Name Value R/W Description
1
CKS1
0
R/W Clock Select 1 and 0
0
CKS0
0
R/W These bits select the internal clock source of the on-chip
baud rate generator. Four clock sources are available. Pφ,
Pφ/4, Pφ/16 and Pφ/64. For further information on the clock
source, bit rate register settings, and baud rate, see section
16.3.8, Bit Rate Register 2 (SCBRR2).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
16.3.6 Serial Control Register 2 (SCSCR2)
The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial
clock output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR2.
Initial
Bit Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty interrupt
(TXI) requested when the serial transmit data is transferred
from the SCFTDR2 to SCTSR2, and the quantity of data in
the SCFTDR2 becomes less than the specified number of
transmission triggers, and then the TDFE flag in the
SCSSR2 is set to1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
disabled.
Note: The TXI interrupt request can be cleared by writing
the greater quantity of transmit data than the specified
number of transmission triggers to SCFTDR2 and by
clearing TDFE to 0 after reading 1 from TDFE, or can be
cleared by clearing TIE to 0.
1: Transmit-FIFO-data-empty interrupt request (TXI) is
enabled.
Rev. 5.00 May 29, 2006 page 449 of 698
REJ09B0146-0500