SH7706 Datasheet, PDF (527/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
1
Serial
data
Start
bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
0 D0 D1
D ₇ 0/1 1 0 D ₀ D ₁
D ₇ 0/1 1
1
Idling
(marking)
RDF
FER
RXI interrupt
request
One frame
Data read and RDF
flag read as 1 then
cleared to 0 by
RXI interrupt handler
ERI interrupt
request generated
by receive error
Figure 16.11 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is full. When
RTS2 is 0, reception is possible. When RTS2 is 1, this indicates that SCFRDR2 is full and
reception is not possible.
Figure 16.12 shows an example of the operation when modem control is used.
Serial
data
RXD2
Start
bit
0 D0 D1 D2
Parity bit
D7 0/1 1
Start
0
RTS2
Figure 16.12 Example of Operation Using Modem Control (RTS2)
Rev. 5.00 May 29, 2006 page 479 of 698
REJ09B0146-0500