SH7706 Datasheet, PDF (282/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.5.5 Burst ROM Interface
Setting bits A0BST (1 to 0), A5BST (1 to 0), and A6BST (1 to 0) in BCR1 to a non-zero value
allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-
speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM
is shown in figure 8.28. Two wait cycles are set. Basically, access is performed in the same way as
for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address
is changed before the next access is executed. When 8-bit ROM is connected, the number of
consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1 to 0), A5BST (1 to 0), or A6BST
(1 to 0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is
connected, only 4 can be set.
WAIT pin sampling is performed in the first access if one or more wait states are set, and is
always performed in the second and subsequent accesses.
The second and subsequent access cycles also comprise two cycles when a burst ROM setting is
made and the wait specification is 0. The timing in this case is shown in figure 8.29.
However, the WAIT signal is ignored in the following cases:
• In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address
area
• In 16-byte DMA transfer or single addressing mode, or when transferring data from an
external device with DACK to the external bus area
• When accessing cache for write back
Rev. 5.00 May 29, 2006 page 234 of 698
REJ09B0146-0500