SH7706 Datasheet, PDF (175/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
11
IRQ51S 0
10
IRQ50S 0
R/W IRQ5 Sense Select
R/W Select whether the interrupt signal to the IRQ5 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ5 input
falling edge
01: An interrupt request is detected at IRQ5 input
rising edge
10: An interrupt request is detected at IRQ5 input
low level
11: Reserved (Setting prohibited)
9
IRQ41S 0
R/W IRQ4 Sense Select
8
IRQ40S 0
R/W Select whether the interrupt signal to the IRQ4 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ4 input
falling edge
01: An interrupt request is detected at IRQ4 input
rising edge
10: An interrupt request is detected at IRQ4 input
low level
11: Reserved (Setting prohibited)
7
IRQ31S 0
R/W IRQ3 Sense Select
6
IRQ30S 0
R/W Select whether the interrupt signal to the IRQ3 pin
is detected at the rising edge, at the falling edge, or
at low level.
00: An interrupt request is detected at IRQ3 input
falling edge
01: An interrupt request is detected at IRQ3 input
rising edge
10: interrupt request is detected at IRQ3 input low
level
11: Reserved (Setting prohibited)
Rev. 5.00 May 29, 2006 page 127 of 698
REJ09B0146-0500