SH7706 Datasheet, PDF (42/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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PLL Synchronization Settling Time at the Returning from Standby Mode
(Return by IRQ/IRL Interrupt)............................................................................. 617
PLL Synchronization Settling Time when Frequency Multiplication
Rate Modified ...................................................................................................... 618
Reset Input Timing .............................................................................................. 620
Interrupt Signal Input Timing .............................................................................. 620
IRQOUT Timing.................................................................................................. 620
Bus Release Timing ............................................................................................. 621
Pin Drive Timing at Standby ............................................................................... 621
Basic Bus Cycle (No Wait) .................................................................................. 624
Basic Bus Cycle (One Wait) ................................................................................ 625
Basic Bus Cycle (External Wait) ......................................................................... 626
Burst ROM Bus Cycle (No Wait) ........................................................................ 627
Burst ROM Bus Cycle (Two Waits) .................................................................... 628
Burst ROM Bus Cycle (External Wait) ............................................................... 629
Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) .. 630
Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) .. 631
Synchronous DRAM Read Bus Cycle
(Burst Read (Single Read × 4), RCD = 0, CAS Latency = 1, TPC = 1) .............. 632
Synchronous DRAM Read Bus Cycle
(Burst Read (Single Read × 4), RCD = 1, CAS Latency = 3, TPC = 0) .............. 633
Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) ........... 634
Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) ........... 635
Synchronous DRAM Write Bus Cycle
(Burst Mode (Single Write × 4), RCD = 0, TPC = 1, TRWL = 0)....................... 636
Synchronous DRAM Write Bus Cycle
(Burst Mode (Single Write × 4), RCD = 1, TPC = 0, TRWL = 0)....................... 637
Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 1) ......................................... 638
Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 2) ......................................... 639
Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1).... 640
Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1).... 641
Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Same Row Address) ....................................................................... 642
Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0) ................................. 643
Synchronous DRAM Burst Write Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 1) ................................. 644
Rev. 5.00 May 29, 2006 page xlii of xlviii