SH7706 Datasheet, PDF (218/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond
to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0
addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the
address space obtained by adding to it H'20000000 × n (n = 1 to 6). The address range for area 7,
which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n–H'1FFFFFFF + H'20000000 × n (n = 0 to 7) corresponding to the area 7 shadow
space is reserved, so do not use it.
8.3.1 PCMCIA Support
This LSI supports PCMCIA standard interface specifications in physical space areas 5 and 6
(except for WP).
The interfaces supported are basically the "IC memory card interface" and "I/O card interface"
stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1).
Table 8.4 PCMCIA Interface Characteristics
Item
Feature
Access
Random access
Data bus
8/16 bits
Memory type
Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM
Memory capacity
Maximum 32 Mbytes
I/O space capacity
Maximum 32 Mbytes
Others
Dynamic bus sizing of I/O bus width*
The PCMCIA interface can be accessed from the address translation
area or non-address translation area.
Note: * Dynamic bus sizing of I/O bus width is supported only in the little endian mode.
Area 5: H'14000000
Area 5: H'16000000
Area 6: H'18000000
Area 6: H'1A000000
Commom memory/Attribute memory
I/O space
Commom memory/Attribute memory
I/O space
Figure 8.4 PCMCIA Space Allocation
Rev. 5.00 May 29, 2006 page 170 of 698
REJ09B0146-0500