SH7706 Datasheet, PDF (306/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
Description
17
AM
0
(R/W)^*2 Acknowledge Mode
AM specifies whether DACK is output in data read
cycle or in data write cycle in dual address mode.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and
CHCR_3; 0 is read if this bit is read.
0: DACK output in read cycle
16
AL
0
1: DACK output in write cycle
(R/W)^*2 Acknowledge Level
AL specifies the DACK (acknowledge) signal
output is high active or low active.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and
CHCR_3; 0 is read if this bit is read.
0: Low-active output of DACK
1: High-active output of DACK
15
DM1
0
R/W
Destination Address Mode
14
DM0
0
R/W
DM1 and DM0 select whether the DMA
destination address is incremented, decremented,
or left fixed.
00: Fixed destination address (Initial value)
01: Destination address is incremented (+1 in 8-
bit transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-
bit transfer, –2 in 16-bit transfer, –4 in 32-bit
transfer; illegal setting in 16-byte transfer)
11: Reserved (Setting prohibited)
Rev. 5.00 May 29, 2006 page 258 of 698
REJ09B0146-0500