SH7706 Datasheet, PDF (588/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
ADIE
Set*
Set*
ADST A/D conversion starts
ADF
Channel 0 (AN0)
operating
Channel 1 (AN1)
operating
Channel 2 (AN2)
operating
Channel 3 (AN3)
operating
ADDRA
Waiting
Waiting
A/D conversion 1
Waiting
Waiting
ADDRB
Clear*
Set*
Clear
Waiting
A/D conversion result 2
Waiting
Read result
A/D conversion result 1
Read result
A/D conversion result 2
ADDRC
ADDRD
Note: * Downward arrows (↓) indicate instruction execution.
Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
19.6.2 Multi Mode (MULTI = 1, SCN = 0)
Multi mode should be selected when performing multi channel A/D conversions on one or more
channels. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
conversion starts on the first channel in the group (AN0 when CH2 = 0). When two or more
channels are selected, after conversion of the first channel ends, conversion of the second channel
(AN1) starts immediately. When A/D conversions end on the selected channels, the ADST bit is
cleared to 0. The conversion results are transferred for storage into the A/D data registers
corresponding to the channels.
When the mode or analog input channel selection must be changed during A/D conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Rev. 5.00 May 29, 2006 page 540 of 698
REJ09B0146-0500