SH7706 Datasheet, PDF (350/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Note that no problem occurs if the clock ratio for Iφ:Bφ is 1:1 after modification of the bits.
Furthermore, no problem occurs if the frequency multiplication ratio bits (STC[2:0]) are
modified at the same time as IFC[2:0].
These problems may be avoided by either of the following measures.
1. Do not use the DMAC when in sleep mode, or set the clock ratio for Iφ:Bφ to 1:1 before
entering sleep mode.
2. Do not use the DMAC when modifying only the internal clock frequency division ratio bits
(IFC[2:0]) to produce a clock ratio for Iφ:Bφ of other than 1:1.
Rev. 5.00 May 29, 2006 page 302 of 698
REJ09B0146-0500