SH7706 Datasheet, PDF (146/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 4 Exception Processing
SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F, SR.CL = 0. Other SR bits are
undefined.
PC = H'A0000000
• Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not
guaranteed in this case.
• When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address
error does not occur at an LDC instruction that updates the SR register and the following
instruction. This occurrence will be identified as multiple exceptions, and may initiate reset
processing.
Rev. 5.00 May 29, 2006 page 98 of 698
REJ09B0146-0500