SH7706 Datasheet, PDF (296/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
CKIO
A25 to A0
CSm
CSn
BS
T1
T2
Twait
T1
T2
Twait
T1
T2
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification
Area n inter-access wait specification
Figure 8.39 Waits between Access Cycles
8.5.8 Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills or a write back and TAS instruction execution
between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that
are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when
longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated
and bus use is restarted. See Appendix B, Pin Functions, for the pin state when the bus is released.
This LSI sometimes needs to retrieve a bus it has released. For example, when memory generates
a refresh request or an interrupt request internally, this LSI must perform the appropriate
processing. This LSI has a bus request signal (IRQOUT) for this purpose. When it must retrieve
the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the
assertion of the IRQOUT signal and negate the BREQ signal to release the bus. This LSI retrieves
the bus and carries out the processing.
Rev. 5.00 May 29, 2006 page 248 of 698
REJ09B0146-0500