SH7706 Datasheet, PDF (628/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
Software Standby to Manual Reset:
CKIO
RESETM^*1
Oscillation stops
Reset
STATUS
Normal^*4
Standby^*3
Reset^*2
Normal^*4
0 to 20 Bcyc^*5
Notes:
1. When software standby mode is cleared with a manual reset, the WDT does not count.
Keep RESETM low during the PLL’s oscillation settling time.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Standby: LH (STATUS1 low, STATUS0 high)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
Figure 22.6 Software Standby to Manual Reset STATUS Output
Timing for Canceling Sleep Mode
Sleep to Interrupt:
Interrupt request
CKIO
STATUS
Normal^*2
Sleep^*1
Normal^*2
Notes: 1. Sleep: HL (STATUS1 high, STATUS0 low)
2. Normal: LL (STATUS1 low, STATUS0 low)
Figure 22.7 Sleep to Interrupt STATUS Output
Rev. 5.00 May 29, 2006 page 580 of 698
REJ09B0146-0500