SH7706 Datasheet, PDF (180/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.4.6 Interrupt Request Register 2 (IRR2)
The interrupt request register 2 (IRR2) is an 8-bit read-only register that indicates whether A/D
converter, or SCIF interrupt requests are generated.
Bit
7 to 5
4
3
2
1
0
Bit Name Initial Value R/W Description
—
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
ADIR
0
R ADI Interrupt Request
Indicates whether an ADI (ADC) interrupt request is
generated.
0: An ADI interrupt request is not generated
1: An ADI interrupt request is generated
TXI2R
0
R TXI2 Interrupt Request
Indicates whether a TXI2 (SCIF) interrupt request is
generated.
0: TXI2 interrupt request is not generated
1: A TXI2 interrupt request is generated
BRI2R 0
R BRI2 Interrupt Request
Indicates whether a BRI2 (SCIF) interrupt request is
generated.
0: A BRI2 interrupt request is not generated
1: A BRI2 interrupt request is generated
RXI2R 0
R RXI2 Interrupt Request
Indicates whether an RXI2 (SCIF) interrupt request is
generated.
0: An RXI2 interrupt request is not generated
1: An RXI2 interrupt request is generated
ERI2R 0
R ERI2 Interrupt Request
Indicates whether an ERI2 (SCIF) interrupt request is
generated.
0: An ERI2 interrupt request is not generated
1: An ERI2 interrupt request is generated
Rev. 5.00 May 29, 2006 page 132 of 698
REJ09B0146-0500