SH7706 Datasheet, PDF (183/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.5.2 Multiple Interrupts
When multiple interrupts are used, the structure of the interrupt service routine should be as
follows.
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2.
The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the
specific handler.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to the memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4.
6.6 Interrupt Response Time
The time from generation of an interrupt request until interrupt exception processing is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 6.7. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception processing is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
The response time is represented by the clock number of Iφ. Depending on the Pφ phase when an
interrupt is occurred, one clock period of Pφ may vary from the contents of this table.
Rev. 5.00 May 29, 2006 page 135 of 698
REJ09B0146-0500