SH7706 Datasheet, PDF (589/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 19.6 shows a timing diagram for this example.
1. Multi mode is selected (MULTI = 1, SCN = 0), channel group 0 is selected (CH2 = 0), analog
input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started
(ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this
time.
When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1,
A/D conversion starts again from the first channel (AN0).
ADST
ADF
Channel 0 (AN0)
operating
Channel 1 (AN1)
operating
Channel 2 (AN2)
operating
Channel 3 (AN3)
operating
ADDRA
ADDRB
ADDRC
ADDRD
Set*
A/D conversion
Clear*
Clear*
Waiting
A/D conversion 1
Waiting
Waiting
A/D conversion 2
Waiting
Waiting
A/D conversion 3
Waiting
Transfer
A/D conversion result 1
Waiting
A/D conversion result 2
A/D conversion result 3
Note: * Downward arrows (↓) indicate instruction executed by software.
Figure 19.6 Example of A/D Converter Operation (Multi Mode,
Channels AN0 to AN2 Selected)
Rev. 5.00 May 29, 2006 page 541 of 698
REJ09B0146-0500