SH7706 Datasheet, PDF (277/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
1. Auto-Refreshing
Figure 8.24 shows the auto-refreshing operation.
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to 0
in RTCSR, and the value set in RTCOR. The value of bits CKS2 to 0 in RTCOR should be set
so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the
settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2
to CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up
from the value at that time. The RTCNT value is constantly compared with the RTCOR value,
and if the two values are the same, a refresh request is generated and an auto-refresh is
performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure
8.25 shows the auto-refresh cycle timing.
All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr
cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new
command output cannot be performed for the duration of the number of cycles specified by the
TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS
and TPC bits must be set so as to satisfy the synchronous DRAM refresh cycle time stipulation
(active/active command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual
reset.
RTCNT value
RTCOR
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
RTCSR.CKS(2 to 0)
CMF
External bus
= 000
≠ 000
CMF flag cleared by start of
refresh cycle
Auto-refresh cycle
Figure 8.24 Auto-Refresh Operation
Time
Rev. 5.00 May 29, 2006 page 229 of 698
REJ09B0146-0500