SH7706 Datasheet, PDF (232/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Table 8.6 Area 6 Wait Control (Normal Memory I/F)
WCR2's bits
Bit 15: Bit 14: Bit 13:
A6W2 A6W1 A6W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
Table 8.7 Area 5 Wait Control (Normal Memory I/F)
WCR2's bits
Bit 12: Bit 11: Bit 10:
A5W2 A5W1 A5W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
Rev. 5.00 May 29, 2006 page 184 of 698
REJ09B0146-0500