SH7706 Datasheet, PDF (581/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 19 A/D Converter (ADC)
19.3.2 A/D Control/Status Register (ADCSR)
ADCSR is an 8-bit read/write register that selects the mode and controls the A/D converter.
Bit
Bit Name Initial Value R/W
Description
7
ADF
0
R/(W)^*1 A/D End Flag
Indicates the end of A/D conversion.
0: [Clearing conditions]
1. Cleared by reading ADF while ADF = 1, then
writing 0 in ADF
2. Cleared when DMAC is activated by ADI
interrupt and ADDR is read
6
ADIE
0
1: [Setting conditions]
1. Single mode: A/D conversion ends
2. Multi mode: A/D conversion ends in all
selected channels
3. Scan mode: A/D conversion ends in all
selected channels.
R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested
at the end of A/D conversion. Set the ADIE when
convertion is stopped.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
Rev. 5.00 May 29, 2006 page 533 of 698
REJ09B0146-0500