SH7706 Datasheet, PDF (611/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 21 User Debugging Interface (H-UDI)
21.4.3 H-UDI Reset
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset
negate command.
The interval required between the H-UDI reset assert command and the H-UDI reset negate
command is the same as the time for which the RESETP pin is held low in order to execute a
power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Branch to H'A0000000
Figure 21.3 H-UDI Reset
21.4.4 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
H-UDI interrupts are not accepted in sleep mode or standby mode.
21.4.5 Bypass
The JTAG-based bypass mode for the H-UDI pins can be selected by setting a command from the
H-UDI in the SDIR.
21.4.6 Using H-UDI to Recover from Sleep Mode
It is possible to recover from sleep mode by setting a command (0001) from the H-UDI in SDIR.
Rev. 5.00 May 29, 2006 page 563 of 698
REJ09B0146-0500