SH7706 Datasheet, PDF (452/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for
transmitting multiprocessor serial data. Transmission of multiprocessor serial data should be
carried out in the following procedure after setting the SCI in a transmission-enabled state.
Start transmission
Read TDRE bit in SCSSR
No
TDRE = 1?
Yes
Write transmission data to SCTDR
and set MPBT bit in SCSSR
Clear TDRE bit to 0
Transmission ended?
No
Yes
Read TEND bit in SCSSR
TEND = 1?
No
Yes
No
Break output?
Yes
Set SCPDR and SCPCR
Clear TE bit SCSCR to 0
1. SCI status check and transmit
data write: Read the SCSSR,
check that the TDRE bit is 1,
then write transmit data in the
SCTDR. Also set MPBT
(multiprocessor bit transfer) to
0 or 1 in SCSSR. Finally, clear
TDRE to 0.
2. To continue transmitting serial
data: Read the TDRE bit to check
whether it is safe to write
(if it reads 1); if so, write data in
SCTDR, then clear TDRE to 0.
3. To output a break at the end of
serial transmission: Set the
SCPDR and SCPCR, then clear
the TE bit to 0 in SCSCR. For
SCPCR and SCPDR settings,
see section 14.3.8, SC Port Control
Register (SCPCR), and section
14.3.9, SC Port Data Register
(SCPDR).
End transmission
Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data
Rev. 5.00 May 29, 2006 page 404 of 698
REJ09B0146-0500