SH7706 Datasheet, PDF (632/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
CKIO
CA
RESETP
STATUS
Standby^*2
Normal^*3
Standby^*2
Undefined
Reset^*1
WDT operation
0 to 10 Bcyc*⁴
2 Rcyc or more^*5
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Standby: LH (STATUS1 low, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) cycle
Figure 22.11 Hardware Standby Mode Timing
(When CA Goes Low during WDT Operation on Standby Mode Cancellation)
Rev. 5.00 May 29, 2006 page 584 of 698
REJ09B0146-0500