SH7706 Datasheet, PDF (462/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Receiving Serial Data (Clock Synchronous Mode): Figure 14.21 shows a sample flowchart for
receiving serial data. Serial data reception should be carried out in the procedure described below
after setting the SCI in a reception-enabled state. When switching from the asynchronous mode to
the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or
FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
Start reception
Read ORER bit in SCSSR
Yes
ORER = 1?
No
Read RDRF bit in SCSSR
Error processing
No
RDRF = 1?
Yes
Read receive data in SCRDR and
clear RDRF bit in SCSSR to 0
No
ORER = 1?
Yes
Overrun error processing
No
All data received?
Yes
Clear RE bit in SCSCR to 0
End reception
Clear ORER bit in SCSSR to 0
End
1. Receive error processing: If a receive error occurs, read the ORER bit in
SCSSR to identify the error. After executing the necessary error processing,
clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1.
2. SCI status check and receive data read: Read the SCSSR, check that RDRF is
set to 1, then read receive data from the SCRDR and clear RDRF to 0. The RXI
interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the
frame MSB (bit 7) of the current frame is received.
Figure 14.21 Sample Flowchart for Serial Data Receiving
Rev. 5.00 May 29, 2006 page 414 of 698
REJ09B0146-0500