SH7706 Datasheet, PDF (310/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
Description
1
TE
0
R/(W)^*1 Transfer End
TE is set to 1 when data transfer ends by the
count specified in DMATCR. At this time, if the IE
bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due
to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this
bit is not set to 1. Even if the DE bit is set to 1
while this bit is set to 1, transfer is not enabled.
0: Data transfer does not end by the count
specified in DMATCR
Clear condition: Writing 0 after TE = 1 read at
power-on reset or manual reset
1: Data transfer ends by the specified count
0
DE
0
R/W
DMAC Enable
DE enables channel operation.
0: Disables channel operation
1: Enables channel operation
Note: If an auto request is specifies (specified in
RS3 to RS0), transfer starts when this bit
is set to 1. In an external request or an
internal module request, transfer starts if
transfer request is generated after this bit
is set to 1. Clearing this bit during transfer
can terminate transfer.
Even if the DE bit is set, transfer is not
enabled if the TE bit is 1, the DME bit in
DMAOR is 0, or the NMIF bit in DMAOR is
1.
Notes: 1. Only 0 can be written to the TE bit after 1 is read.
2. DI, RO, RL, AM, AL, and DS bits are not included in some channels.
Rev. 5.00 May 29, 2006 page 262 of 698
REJ09B0146-0500