SH7706 Datasheet, PDF (27/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

8.4.7 Synchronous DRAM Mode Register (SDMR) .................................................... 193
8.4.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 193
8.4.9 Refresh Timer Counter (RTCNT)........................................................................ 196
8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 196
8.4.11 Refresh Count Register (RFCR) .......................................................................... 197
8.5 Operation .......................................................................................................................... 197
8.5.1 Endian/Access Size and Data Alignment............................................................. 197
8.5.2 Description of Areas ............................................................................................ 202
8.5.3 Basic Interface ..................................................................................................... 205
8.5.4 Synchronous DRAM Interface............................................................................. 211
8.5.5 Burst ROM Interface............................................................................................ 234
8.5.6 PCMCIA Interface ............................................................................................... 236
8.5.7 Waits between Access Cycles.............................................................................. 247
8.5.8 Bus Arbitration .................................................................................................... 248
8.5.9 Bus Pull-Up.......................................................................................................... 249
Section 9 Direct Memory Access Controller (DMAC) ............................................ 251
9.1 Feature .............................................................................................................................. 251
9.2 Input/Output Pin................................................................................................................ 254
9.3 Register Description.......................................................................................................... 254
9.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ................................ 255
9.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)........................ 255
9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)............... 256
9.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)......................... 256
9.3.5 DMA Operation Register (DMAOR)................................................................... 263
9.4 Operation .......................................................................................................................... 265
9.4.1 DMA Transfer Flow ............................................................................................ 265
9.4.2 DMA Transfer Requests ...................................................................................... 267
9.4.3 Channel Priority ................................................................................................... 269
9.4.4 DMA Transfer Types........................................................................................... 272
9.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 284
9.4.6 Source Address Reload Function ......................................................................... 288
9.4.7 DMA Transfer Ending Conditions....................................................................... 290
9.5 Compare Match Timer (CMT).......................................................................................... 292
9.5.1 Feature ................................................................................................................. 292
9.5.2 Register Description............................................................................................. 293
9.5.3 Operation ............................................................................................................. 295
9.6 Examples of Use ............................................................................................................... 298
9.6.1 Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on) ............................................................................................ 298
Rev. 5.00 May 29, 2006 page xxvii of xlviii