SH7706 Datasheet, PDF (343/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Compare Match Counter (CMCNT)
The compare match counter (CMCNT) is a 16-bit register used as an up-counter.
When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR and the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT value matches that of the CMCOR, the CMCNT is cleared to H'0000 and the CMF flag
of the CMCSR is set to 1.
The CMCNT0 is initialized to H'0000 by resets. It retains its previous value in standby mode.
Compare Match Constant Register (CMCOR)
The compare match constant register (CMCOR) is a 16-bit register that sets the compare match
period with the CMCNT.
The CMCOR is initialized to H'FFFF by resets. It retains its previous value in standby mode.
9.5.3 Operation
Period Count Operation
When a clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR0 bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the CMCOR, the CMCNT counter is cleared to H'0000
and the CMF flag of the CMCSR register is set to 1. The CMCNT counter begins counting up
again from H'0000.
Figure 9.27 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Time
Figure 9.27 Counter Operation
Rev. 5.00 May 29, 2006 page 295 of 698
REJ09B0146-0500