SH7706 Datasheet, PDF (311/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.5 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC
transfer mode.
This register's values are initialized to 0s by resets. The previous value is held in standby mode.
Bit
Bit Name
15 to 10 —
9
PR1
8
PR0
7 to 3 —
2
AE
Initial Value R/W Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W Priority Mode
0
R/W PR1 and PR0 select the priority level between
channels when there are transfer requests for
multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: CH2 > CH0 > CH1 > CH3
11: Round-robin
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/(W)* Address Error Flag
AE indicates that an address error occurred during
DMA transfer. If this bit is set during data transfer,
transfers on all channels are suspended. The
CPU cannot write 1 to this bit.
0: No DMAC address error. DMA transfer is
enabled.
Clearing conditions: Writing AE = 0 after AE = 1
read, power-on reset, manual reset
1: DMAC address error. DMA transfer is disabled.
Setting condition: This bit is set by occurrence
of a DMAC address error.
Rev. 5.00 May 29, 2006 page 263 of 698
REJ09B0146-0500