SH7706 Datasheet, PDF (212/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
 Bus sizing function for I/O bus width (only in the little endian mode)
• Refresh function
 Refresh cycles will be automatically maintained in the sleep mode even after the external
bus frequency is reduced to 1/4 of its normal operating frequency
• The refresh counter can be used as an interval timer
 Outputs an interrupt request signal using the compare-matching function
 Outputs an interrupt request signal when the refresh counter overflows
WAIT
Wait
controller
WCR1
WCR2
Bus
interface
CS0, CS6 to CS2,
CE2A, CE2B
BS
RD
RD/WR
WE3 to WE0
RASx
CASx
CKE
ICIORD, ICIOWR
IOIS16
Interrupt
controller
Area
controller
Memory
controller
Refresh
controller
BCR1
BCR2
MCR
PCR
RFCR
RTCNT
Comparator
RTCOR
RTCSR
Legend:
WCR : Wait state control register
BCR : Bus control register
MCR : Memory control register
PCR : PCMCIA control register
BSC
RFCR : Refresh count register
RTCNT : Refresh timer count register
RTCOR : Refresh time constant register
RTCSR : Refresh timer control/status register
Figure 8.1 BSC Functional Block Diagram
Rev. 5.00 May 29, 2006 page 164 of 698
REJ09B0146-0500