SH7706 Datasheet, PDF (322/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
CSn
D31 to D0
Transfer source
address
Transfer destination
address
RD
WEn
DACKn
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of CSn.
Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Rev. 5.00 May 29, 2006 page 274 of 698
REJ09B0146-0500