SH7706 Datasheet, PDF (172/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE)
The interrupt priority level setting registers A to E (IPRA to IPRE) are 16-bit read/write registers
that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are
initialized to H'0000 at power-on reset, manual reset, or in hardware standby mode, but is not
initialized in standby mode.
Table 6.6 lists the relationship between the interrupt sources and the IPRA to IPRE bits.
Table 6.6 Interrupt Request Sources and IPRA to IPRE
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
IPRA
TMU0
TMU1
TMU2
IPRB
WDT
REF
SCI0
IPRC
IRQ3
IRQ2
IRQ1
IPRD
Reserved*
Reserved*
IRQ5
IPRE
DMAC
Reserved*
SCIF
Note: * These bits are always read as 0. The write value should be 0.
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
ADC
As shown in table 6.6, four sets of on-chip peripheral module, IRQ interrupts are assigned to each
register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values
from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is
priority level 15 (the highest level). A reset initializes IPRA to IPRE to H'0000.
H'0 should be set into bits corresponding to an unused interrupt.
Rev. 5.00 May 29, 2006 page 124 of 698
REJ09B0146-0500