SH7706 Datasheet, PDF (12/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
Page
8.4.6 PCMCIA
192
Control Register (PCR)
Table 8.10 Area 6
Wait Control (PCMCIA
I/F)
8.5.4 Synchronous 222
DRAM Interface
Figure 8.24 Auto-
229
Refresh Operation
Revision (See Manual for Details)
Table title amended
Description added
If an external bus access request (in order to perform 2) below
conflicts with an auto-refresh request, self-refresh request, or
bus release request internal to the LSI under the following
conditions, SDRAM all-bank precharge may not be executed
properly in the first cycle of the refresh or bus release cycle. In
this case, precharging of the selected bank is executed instead
of all-bank precharge.
1. The RASD bit in the individual memory control register
(MCR) is set to 1
and
2. long-word access is performed to any 16-bit bus width area
(areas 0 to 6) or word/long-word access is performed to any 8-
bit bus width area (areas 0 to 6).
The problem may be avoided by either of the following
measures.
1. Use the auto-precharge mode.
2. Use 32-bit bus width for all areas.
Figure amended
RTCNT value
RTCOR
H'00000000
Rev. 5.00 May 29, 2006 page xii of xlviii