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SH7706 Datasheet, PDF (62/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series
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Section 2 CPU
Switching between user mode and privileged mode is controlled by the processor mode bit (MD)
in the status register.
31
0
R0_BANK0*1 *2
R1_BANK0*2
R2_BANK0*2
R3_BANK0*2
R4_BANK0*2
R5_BANK0*2
R6_BANK0*2
R7_BANK0*2
R8
R9
R10
R11
R12
R13
R14
R15
SR
GBR
MACH
MACL
PR
PC
a. User mode register
configuration
31
0 31
0
R0_BANK1*1 *3
R0_BANK0*1 *4
R1_BANK1*3
R1_BANK0*4
R2_BANK1*3
R2_BANK0*4
R3_BANK1*3
R3_BANK0*4
R4_BANK1*3
R4_BANK0*4
R5_BANK1*3
R5_BANK0*4
R6_BANK1*3
R6_BANK0*4
R7_BANK1*3
R7_BANK0*4
R8
R8
R9
R9
R10
R10
R11
R11
R12
R12
R13
R13
R14
R14
R15
R15
SR
SSR
SR
SSR
GBR
MACH
MACL
PR
VBR
GBR
MACH
MACL
PR
VBR
PC
SPC
R0_BANK0*1 *4
R1_BANK0*4
R2_BANK0*4
R3_BANK0*4
R4_BANK0*4
R5_BANK0*4
R6_BANK0*4
R7_BANK0*4
b. Privileged mode
register configuration
(RB = 1)
PC
SPC
R0_BANK1*1 *3
R1_BANK1*3
R2_BANK1*3
R3_BANK1*3
R4_BANK1*3
R5_BANK1*3
R6_BANK1*3
R7_BANK1*3
c. Privileged mode
register configuration
(RB = 0)
Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed
GBR-indirect addressing mode.
2. Banked register
3. Banked register
When the RB bit of the SR register is 1, the register can be accessed for general use. When the
RB bit is 0, it can only be accessed with the LDC/STC instruction.
4. Banked register
When the RB bit of the SR register is 0, the register can be accessed for general use. When the
RB bit is 1, it can only be accessed with the LDC/STC instruction.
Figure 2.1 Register Configuration
Rev. 5.00 May 29, 2006 page 14 of 698
REJ09B0146-0500
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