SH7706 Datasheet, PDF (556/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 18 I/O Ports
18.1.2 Port A Data Register (PADR)
Port A data Register (PADR) is an 8-bit read/write register that stores data for pins PTA7 to
PTA0. PA7DT to PA0DT bit corresponds to PTA7 to PTA0 pin. When the pin function is general
output port, if the port is read the value of the corresponding PADR bit is returned directly. When
the function is general input port, if the port is read the corresponding pin level is read.
Bit
Bit Name Initial Value R/W Description
7
PA7DT
0
R/W Table 18.1 shows the function of PADR.
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
Table 18.1 Read/Write Operation of the Port A Data Register (PADR)
PAnMD1 PAnMD0 Pin State
Read
Write
0
0
Other function PADR value Value is written to PADR, but does not affect
pin state.
1
Output
PADR value Write value is output from pin.
1
0
Input (Pull-up Pin state
MOS on)
Value is written to PADR, but does not affect
pin state.
1
Input (Pull-up Pin state
Value is written to PADR, but does not affect
MOS off)
pin state.
Note: n = 0 to 7
Rev. 5.00 May 29, 2006 page 508 of 698
REJ09B0146-0500