SH7706 Datasheet, PDF(299/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (299/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 9 Direct Memory Access Controller (DMAC)

Section 9 Direct Memory Access Controller (DMAC)

This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be

used in place of the CPU to perform high-speed transfers between external devices that have

DACK (transfer request acknowledge signal), external memory, memory-mapped external

devices, and on-chip peripheral modules (SCIF, A/D converter, and D/A converter). Using the

DMAC reduces the burden on the CPU and increases overall operating efficiency.

Figure 9.1 shows a block diagram of the DMAC.

9.1 Feature

The DMAC has the following features.

â¢ Four channels

â¢ Address space: Architecturally 4-Gbytes

â¢ 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer, four 32-bit reads are executed,

followed by four 32-bit writes.)

â¢ Maximum transfer counter: 16 Mbytes (16777216 transfers)

â¢ Supports dual address mode

ï£§ Direct address transfer mode: The values specified in the DMAC registers indicates the

transfer source and transfer destination. Two bus cycles are required for one data transfer.

ï£§ Indirect address transfer mode: Data is transferred with the address stored prior to the

address specified in the transfer source address in the DMAC. Other operations are the

same as those of direct address transfer mode. This function is only valid in channel 3. Four

bus cycles are required for one data transfer.

â¢ Supports single address mode

ï£§ Either the transfer source or transfer destination peripheral device is accessed (selected) by

means of the DACK signal, and the other device is accessed by address. One bus cycle is

required for one data transfer.

â¢ Channel functions: Transfer mode that can be specified is different in each channel.

ï£§ Channel 0: External request can be accepted.

ï£§ Channel 1: External request can be accepted.

ï£§ Channel 2: This channel has a source address reload function, which reloads a source

address for each 4 transfers.

ï£§ Channel 3: In this channel, direct address transfer mode or indirect address transfer mode

can be specified.

Rev. 5.00 May 29, 2006 page 251 of 698

REJ09B0146-0500

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