SH7706 Datasheet, PDF (564/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 18 I/O Ports
18.5.2 Port E Data Register (PEDR)
Port E data register (PEDR) is an 8-bit read/write register that stores data for pins PTE7 to PTE0.
PE7DT to PE0DT bit corresponds to PTE7 to PTE0 pin. When the pin function is general output
port, if the port is read the value of the corresponding PEDR bit is returned directly. When the
function is general input port, if the port is read the corresponding pin level is read.
PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pull-
up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains
its previous value in standby mode and sleep mode, and in a manual reset.
Bit
Bit Name Initial Value R/W Description
7
PE7DT
0
R/W Table 18.5 shows the function of PEDR.
6
PE6DT
0
R/W
5
PE5DT
0
R/W
4
PE4DT
0
R/W
3
PE3DT
0
R/W
2
PE2DT
0
R/W
1
PE1DT
0
R/W
0
PE0DT
0
R/W
Table 18.5 Read/Write Operation of the Port E Data Register (PEDR)
PEnMD1 PEnMD0 Pin State
Read
Write
0
0
Other function PEDR value Value is written to PEDR, but does not affect
pin state.
1
Output
PEDR value Write value is output from pin.
1
0
Input (Pull-up Pin state
MOS: on)
Value is written to PEDR, but does not affect
pin state.
1
Input (Pull-up Pin state
Value is written to PEDR, but does not affect
MOS: off)
pin state.
Note: n = 0 to 7
Rev. 5.00 May 29, 2006 page 516 of 698
REJ09B0146-0500