SH7706 Datasheet, PDF (498/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive-data-full (RXI) and receive-
error (ERI) interrupts requested when the serial receive
data is transferred from the SCRSR2 to SCFRDR2, when
the quantity of data in the SCFRDR2 becomes more than
the specified number of receive triggers, and when the
RDRF flag of SCSSR2 is set to1.
0: Receive-data-full interrupt (RXI), receive-error interrupt
(ERI), and receive break interrupt (BRI) requests are
disabled.
Note: RXI and ERI interrupt requests can be cleared by
reading the DR, ER, or RDF flag after it has been set to
1, then clearing the flag to 0, or by clearing RIE to 0. At
RDF, read 1 from the RDF flag and clear it to 0, after
reading the received data from SCFRDR2 until the
quantity of received data becomes less than the
specified number of the receive triggers.
1: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are enabled.
5
TE
0
R/W Transmit Enable
Enables or disables the SCIF serial transmitter.
0: Transmitter disabled.
1: Transmitter enabled.
Note: Serial transmission starts after writing of transmit
data into the SCFTDR2. Select the transmit format in the
SCSMR2 and SCFCR2 and reset the TFIFO before
setting TE to 1.
4
RE
0
R/W Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled.
Note: Clearing RE to 0 does not affect the receive flags
(DR, ER, BRK, FER and PER). These flags retain their
previous values.
1: Receiver enabled.
Note: Serial reception starts when a start bit is detected.
Select the receive format in the SCSMR2 before setting
RE to 1.
Rev. 5.00 May 29, 2006 page 450 of 698
REJ09B0146-0500